1. Field of the Invention
Example embodiments of the present invention relate to charge pump circuits and methods for the same.
2. Description of the Related Art
Related art charge pump circuits may charge a capacitor at one node using a driver while concurrently discharging a capacitor at a neighboring node. In these related art charge pump circuits, charge consumption may be proportional to the product of a capacitance and a supply voltage, and may be reduced by charging through one node, pre-discharging (or pre-charging) through the neighboring node before discharging through a ground node, and completing the discharge through the ground node after disconnecting from the neighboring node.
If charge pumping is performed by alternating the charge operation with the pre-charge operation, the pre-charge may first be performed from the node in the charge operation, the remaining charge may then be provided from an external voltage source, and the amount of charge consumed in the charge operation may be reduced.
FIG. 1 is a block diagram of a related art voltage generation circuit 10. Referring to FIG. 1, the voltage generation circuit 10 may include an oscillator 11, a clock generator 12, a charge pump circuit 13 and a regulator 14. The oscillator (e.g., a ring oscillator) 11 may generate an oscillation signal OSC for triggering an operation of the clock generator 12, which may be enabled (e.g., started, triggered, etc.) by an enable signal EN. The clock generator 12 may be triggered by the oscillation signal OSC, and may generate clock signals for controlling the operation of the charge pump circuit 13. The charge pump circuit 13 may include a plurality of charge pump cells and may perform a charge pumping operation by alternating a charge and discharge operation based on the clock signals output from the clock generator 12 to output a higher voltage for a semiconductor circuit. The regulator 14 may output a reset signal RST for deactivating (e.g., turning off) the oscillator 11, for example, when the voltage output from the charge pump circuit 13 reaches a threshold level (e.g., a desired level). The regulator 14 may control the operation of the oscillator 11 such that the output voltage of the charge pump circuit 13 may reach the threshold level (e.g., desired level).
FIG. 2 is a circuit diagram of a related art charge pump circuit 20. FIG. 3 is a timing diagram of clock signals for driving the related art charge pump circuit 20 shown in FIG. 2.
FIG. 2 illustrates a portion of a plurality of charge pump cells of the related art charge pump circuit 20. The charge pump circuit 20 may generate a higher voltage by pumping charge using the charge pump cells connected in series as shown in FIG. 2. Referring to FIG. 2, the charge pump circuit 20 may pull-up charge input through a capacitor (e.g., a pumping capacitor) Cp for charge pumping to a higher voltage and may output the pull-up voltage to a next cell. For example, when the charge pump circuit 20 drives the capacitor Cp connected to a voltage output node N(i) of an ith cell to a higher voltage using a charge clock signal nPh1 and pulls up a switching clock signal Ph1a to a higher level, charge from the voltage output node N(i) of the ith cell may move to an output node N(i+1) of an (i+1)th cell. The capacitor Cp, a first parasitic capacitor Cc and a second parasitic capacitor Cs may be driven by charge clock signals nPh1 and nPh2. The first parasitic capacitor Cc may have a parasitic capacitance of the capacitor Cp when the pumping capacitor Cp operates, and the second parasitic capacitor Cs may have another capacitance (e.g., a stray capacitance), which may also be the parasitic capacitance of each node.
The amount of charge consumed when the charge pumping is performed in the charge pump circuit 20 may be on average Vdd×(Cp+Cc)×N, where N denotes the number of charge pump cells. The charge pumping efficiency E is E=Q_load/Q_consumed={Cp/(Cp+Cs)×(N+1)×Vdd−V_target}/{N2×Vdd×(Cp+Cc)}, where Q_load denotes the amount of charge supplied to a load, for example, the output node, Q_consumed denotes the amount of charge consumed in the pumping operation, Vdd denotes an input voltage, V_target denotes an output voltage of the load, and N denotes the number of charge pump cells.
The first and second parasitic capacitors Cc and Cs may be removed to increase (e.g., maximize) the charge pumping efficiency E. The capacitance of the first and second parasitic capacitors Cc and Cs may be determined by a charge supplying scheme and by the configuration of the pumping capacitor Cp.
In related art charge pumping methods, charge used to charge the pumping capacitor Cp may be subsequently discharged. In order to reduce the amount of charge discharged and increase the charge pumping efficiency E, related art charge pump circuits may share charge in one pumping capacitor with a neighboring capacitor before discharging the pumping capacitor.
FIG. 4 is a circuit diagram of a related art charge pump circuit 40 capable of distributing charge. FIG. 5 is a timing diagram of clock signals for driving the charge pump circuit 40 shown in FIG. 4.
When the charge pump circuit 40 charges or discharges an output node N(i) of an ith cell and an output node N(i+1) of an (i+1)th cell using the clock signals shown in FIG. 5, the charge pump circuit 40 may reduce the consumption of charge by sharing the initial charge at each node and charging or discharging to compensate for the shortage or excess of charge. For example, when the clock of a pumping capacitor Cp connected to the output node N(i) of the ith cell is 0V and the clock of a pumping capacitor Cp connected to the output node N(i+1) of the (i+1)th cell is Vdd, the charge of the pumping capacitors connected to the output node N(i) and the output node N(i+1) may be shared by enabling a pre-charge clock signal Ph3 to Vdd, before the pumping capacitor Cp connected to the output node N(i) is charged and the pumping capacitor Cp connected to the output node N(i+1) is discharged. In the related art, pre-charging may increase the voltage of the output node N(i) to Vdd/2 by sharing the charge with the neighboring node N(i+1), and the voltage of the output node N(i+1) may decrease to Vdd/2. By supplying Vdd to the pumping capacitor Cp connected to the output node N(i), and 0V to the pumping capacitor Cp connected to the output node N(i+1), after disabling the pre-charge clock signal Ph3 to 0V, the pumping capacitor Cp connected to the output node N(i) may be charged from Vdd/2 to Vdd, the pumping capacitor Cp connected to the output node N(i+1) may be discharged from Vdd/2 to 0V, and the charge pump circuit 40 may consume a reduced amount of charge.
The related art charge pump circuit 40 may suppress the inversely flowing charge from the output node N(i+1) to the output node N(i) by keeping a charge supply transistor 42 inactive (e.g., off) during pre-charging.
FIG. 6 illustrates a related art charge pump circuit 60 during a pre-charge operation.
In the related art charge pump circuit 60 shown in FIG. 6, the pumping capacitor Cp may be connected in series with the second parasitic capacitor Cs. The amount of charge shared to each node may be Vdd/2×[Cc+{Cp×Cs/(Cp+Cs)}]. In the related art, the capacitance of the second parasitic capacitor Cs of each node of the charge pump circuit 60 may decrease the pumping efficiency. Further, since the capacitance of the parasitic capacitors Cc and Cs is smaller relative to the pumping capacitor Cp, the amount of shared charge is Vdd/2×(Cc+Cs) and the increase in pumping efficiency may be limited (e.g., insubstantial).